1. Field of the Invention
The invention relates to the process of designing and fabricating semiconductor chips. More specifically, the invention relates to a method and an apparatus for automatically resolving conflicts between phase shifters during creation of a mask to be used in an optical lithography process for manufacturing an integrated circuit.
2. Related Art
Recent advances in integrated circuit technology have largely been accomplished by decreasing the feature size of circuit elements on a semiconductor chip. As the feature size of these circuit elements continues to decrease, circuit designers are forced to deal with problems that arise as a consequence of the optical lithography process that is typically used to manufacture integrated circuits. This optical lithography process generally begins with the formation of a photoresist layer on the surface of a semiconductor wafer. A mask composed of opaque regions, which are generally formed of chrome, and light-transmissive clear regions, which are generally formed of quartz, is then positioned over this photo resist layer coated wafer. (Note that the term xe2x80x9cmaskxe2x80x9d as used in this specification is meant to include the term xe2x80x9creticle.xe2x80x9d) Light is then shone on the mask from a visible light source or an ultraviolet light source.
This light is generally reduced and focused through an optical system that contains a number of lenses, filters and mirrors. The light passes through the clear regions of the mask and exposes the underlying photoresist layer. At the same time, the light is blocked by opaque regions of mask, leaving underlying portions of the photoresist layer unexposed.
The exposed photoresist layer is then developed, typically through chemical removal of the exposed/non-exposed regions of the photoresist layer. The end result is a semiconductor wafer with a photoresist layer having a desired pattern. This pattern can then be used for etching underlying regions of the wafer.
Phase shifters are often incorporated into a mask in order to achieve line widths that are smaller than the wavelength of the light that is used to expose the photoresist layer through the mask. During phase shifting, destructive interference caused by two adjacent clear areas on a mask is used to create an unexposed area on the photoresist layer. This is accomplished by exploiting the fact that light passing through a mask""s clear regions exhibits a wave characteristic having a phase that is a function of the distance the light travels through the mask material. By placing two clear areas adjacent to each other on the mask, one of thickness t1 and the other of thickness t2, one can obtain a desired unexposed area on the underlying photoresist layer caused by interference. By varying the thickness t1 and t2 appropriately, the light exiting the material of thickness t2 is 180 degrees out of phase with the light exiting the material of thickness t1. Phase shifting is described in more detail in U.S. Pat. No. 5,858,580, entitled xe2x80x9cPhase Shifting Circuit Manufacture Method and Apparatus,xe2x80x9d by inventors Yao-Ting Wang and Yagyensh C. Pati, filed Sep. 17, 1997 and issued Jan. 12, 1999.
For example, FIG. 1 illustrates how a phase shifter comprised of a zero-degree clear region 104 and a 180-degree clear region 106 is used to achieve a smaller line width for a gate region of a transistor. As circuit dimensions on semiconductor chips become progressively smaller, phase shifters are presently being used to define other critical-dimension features in addition to transistor gates. FIG. 2 illustrates how phase shifters are additionally used to define interconnections between phase shifters. For example, in FIG. 2 phase shifters 210-213 are used to define the gates of four different transistors 202-205 in the circuit layout. However, phase shifters 210-212 additionally extend past these gate regions to additionally define interconnections between the gates. Note that in FIG. 2, phase shifters are represented by diagonal lines, non-phase-shifted features are represented by cross-hatching, phase-shifted regions are clear and diffusion regions are represented by a grid pattern.
As phase shifters are used define more features on a semiconductor chip, coloring conflicts are more likely to arise between phase shifters. Note that phase shifters operate by creating interference patterns between zero-degree clear regions and 180-degree clear regions. Coloring conflicts arise when nearby phase shifting regions have the same phase. For example, when a first zero-degree clear region is in close proximity to a second zero-degree clear region, light from the first clear region reinforces light from the second clear region on the photoresist layer between the first and second clear regions. This can cause unwanted exposure of the photoresist layer.
In order to prevent this problem, systems that lay out phase shifters typically perform tests to ensure that coloring conflicts to not occur. However, as more phase shifting regions are incorporated into a phase shifting mask, it becomes increasingly harder to assign phases to phase shifters so that coloring conflicts do not occur.
A particular problem arises in defining phase shifters to form junctions, such as T-junctions and L-junctions and assigning phase to the same. For example, consider the T-junction 401 illustrated in FIG. 4A. Three phase shifters are used to define this T-junction, including zero-degree region 402, 180-degree region 403 and zero-degree region 404. Note that a coloring violation arises between zero-degree region 402 and zero-degree region 404 on the left-hand side of the T-junction. Furthermore, note that any possible assignment of phases to phase shifters 402-404 also causes a coloring violation.
What is needed is a method and an apparatus for resolving coloring conflicts that arise between phase shifters that arise at T-junctions and/or L-junctions.
One embodiment of the invention provides a system that automatically resolves conflicts between phase shifters during creation of a phase shifting mask to be used in an optical lithography process for manufacturing an integrated circuit. Upon receiving a specification of a layout on the integrated circuit, the system identifies critical-dimension features within the layout. Next, the system places phase shifters comprised of phase shifting geometries on the phase shifting mask to precisely define the critical-dimension features. In doing so, the system identifies junctions within and/or between the critical-dimension features, and removes phase shifting geometries associated with the junctions to obviate coloring conflicts between phase shifters on the phase shifting mask.
In one embodiment of the invention, the junctions include T-junctions and/or L-junctions.
In one embodiment of the invention, the system assigns merit values between phase shifting geometries that potentially conflict. The system subsequently uses these merit values in deciding which phase shifting geometries to remove. In a variation on this embodiment, the system assigns merit values using a rule-based mechanism. In a variation on this embodiment, the system assigns merit values using a model-based mechanism.
In one embodiment of the invention, the system removes phase shifting geometries by performing a coloring operation on the phase shifting geometries. Next, if one or more coloring conflicts are detected during the coloring operation, the system removes phase shifting geometries associated with the junctions to obviate the coloring conflicts.
In one embodiment of the invention, the system removes phase shifting geometries associated with junctions that can potentially give rise to coloring conflicts. Next, the system performs a coloring operation on the remaining phase shifting geometries, and then inserts removed phase shifting geometries back into the phase shifting mask, if it is possible to do so without creating a coloring conflict.
In one embodiment of the invention, the system additionally assigns phases to the phase shifting geometries in a manner that avoids conflicts between phase shifters.
In one embodiment of the invention, the critical-dimension features include transistor gates and critical interconnects.
One embodiment of the invention provides an integrated circuit created through a process that resolves conflicts between phase shifters during creation of a phase shifting mask. This integrated circuit includes critical-dimension features created by using phase shifters comprised of phase shifting geometries on a phase shifting mask. In creating these critical-dimension features, phase shifting geometries for T-junctions are removed to obviate coloring conflicts. In a variation in this embodiment, phase shifting geometries for L-junctions are also removed to obviate coloring conflicts.